Memory & Packaging
HBM, GDDR, and the package the chip ships in.
Qualcomm HBC validation clears 5×, short of the 6× target
Qualcomm's first HBC validation came in at more than five times the bandwidth-per-watt of HBM4, one step below the six-fold efficiency the company projected at its mid-2026 Investor Day.
Qualcomm validates two-layer HBC ahead of 2027 Dragonfly AI250 sampling
A two-layer HBC stack cleared Qualcomm's initial validation ahead of 2027 Dragonfly AI250 sampling.
CXMT clears 4F² 6th-generation DRAM engineering sample
CXMT disclosed verification of an engineering sample for its 4F²-based 6th-generation DRAM platform, with a possible DDR5 RDIMM server sample by year-end.
Samsung ships 12-layer HBM4E samples on May 29, 2026
On May 29, 2026, Samsung said it began shipping 12-layer HBM4E samples at a stable 14 Gbps pin speed, with bandwidth up to 3.6 TB/s per stack.
Samsung sells out 2027 HBM4 supply and starts HBM4E in H1 2027
The 2027 HBM4 book is closed, and Samsung puts HBM4E into mass production in H1 2027.
Patriot DDR5-7600 kit listing rises to $1,523.47 from $109.99
Amazon now asks $1,523.47 for a Patriot Viper Xtreme 5 32GB DDR5-7600 CL36 kit that sold for $109.99 on August 29, 2024.
US price of the arc pro B70 more than doubles
The ASUS Arc Pro B70 launched in Europe at €1,799, and US pricing has since more than doubled to up to $2,400.
TSMC CoWoS price adjustment runs 10% to 20%
TSMC CoWoS pricing is adjusting upward 10% to 20%, per supply-chain sources in the China Times report, as packaging capacity tightens.
Nagare Labs pairs oxide Z2RAM with Gelsinger backing
Nagare Labs says its oxide Z2RAM can put 320 MB in the footprint of a 64 MB SRAM tile, with Gelsinger-linked Playground Global helping fund the seed.
SOCAMM3 targets 2028 CPUs with Nvidia Rosa and AMD Florence
SOCAMM3 is aimed at CPUs from 2028, with Nvidia Rosa and the Rosa Feynman platform named first, and AMD Florence adding LPDDR support at end 2028.
RTX 5080 16 GB China spot price rises 2000 yuan on GDDR7 squeeze
GDDR7 supply pressure is pushing the RTX 5080 16 GB China spot price to 14,500-15,000 yuan, up from 12,700-13,500 yuan.
Micron drops 4F² DRAM and bets on 3D DRAM
Micron's 1δ DRAM node ramps in the second half of 2027 with a mid-20% bit-density gain.
A five-year Tesla supply term is the change in Samsung's substrate expansion
A five-year supply term is the change, while Tesla and NVIDIA fund the build with 3.7 trillion won.
Micron skips G10 and moves G11 to 400-plus layers
G10 is the missing number in Micron's NAND roadmap, with G11 listed at 400-plus layers and mass production in the second half of 2027.
SK hynix adds ICE cooling to HBM package
SK hynix says its iHBM package, with integrated cooling elements in the HBM stack, cuts thermal resistance by 30% for next-generation HBM products.
Groq's next LPU swaps SRAM for 3D stacked DRAM
The next Groq LPU reportedly swaps 500 MB of SRAM for 3D stacked DRAM, raising capacity while leaving bandwidth unmeasured.
CXMT DRAM wafer capacity forecast climbs to 420,000 per month
The step to 420,000 DRAM wafers per month is a consumer DRAM move, not an HBM answer.
NVIDIA's NVHBM base die moves to TSMC 3nm
Samsung is checking whether its own lines can cover NVHBM base-die demand if TSMC capacity runs short, while the base die moves to TSMC's 3nm process.
The RTX 5060 Ti 16GB bandwidth ceiling gives way to a practical range
Decode is weight-bound, so the useful buyer number for the RTX 5060 Ti 16GB is the practical range, not the 448 GB/s bus ceiling.
PS6 memory cost claim jumps past $680
The bill of materials is already near $1,000, and the memory line alone now exceeds a PlayStation 5's retail price.
Huawei LogicFolding sets a 2031 Kirin density target
A 2027 Kirin test met Huawei's internal targets, using LogicFolding stacking with more than 50 million hybrid connections and a 2031 5.00 GHz goal.
Sanctions push CXMT's 4F² DDR5 onto DUV
Rosenblatt calls CXMT's 4F² DDR5 plan a paper tiger, and BofA points to EUV sanctions as the reason.
Morgan Stanley's CoWoS forecast turns 2026 capacity into a schedule constraint
Second-tier ASIC makers get less than 15% of TSMC's 2026 CoWoS capacity in the Morgan Stanley split.
CoWoS capacity, not HBM samples, gates accelerator supply
CoWoS packaging capacity is the limiting step for HBM4E, even though SK hynix and Samsung have shipped 12-layer samples to Nvidia and other customers.
100B phone LLM demand hits a RAM wall
The memory wall is the story. A 4-bit quantized 100B LLM needs 50GB of RAM on a phone, and the brief has no DRAM cost, no supply quantity, no thermal measurement, and no inference speed.
What a gigabyte of HBM4 costs, next to DDR5 at $58.90 a die
TrendForce's spot board, stamped 9 October 2026, averages a DDR5 16Gb die at 58.90 dollars. That public page has no HBM row. A reported HBM4 ask is still not a contract.
Foveros stacking gives the note a shape, but the date decides it
H2 2028 is the fact that turns the Foveros note into a possible NVIDIA backend question, because Intel 14A is expected to enter production then.
Synology neo+ lists below Plus models with non-ECC memory
Synology's neo+ NAS units are listed about 200 euros below the matching Plus models, with 4 GB of non-ECC RAM in the fixed configuration.
Samsung HBM4E qualification claim leaves volumes and production date open
Samsung's 12-high HBM4E stack is rated at 48 GB and up to 3.6 TB/s at 14 Gbit/s per pin, while qualification at Nvidia remains unconfirmed.
Samsung HBM4E sample page stops at 14 Gbps
Samsung's vendor page lists 12-layer HBM4E samples at 14 Gbps per pin, 48 GB per stack, and 3.6 TB/s bandwidth, without naming qualification or supply dates.
MaxLINC holds 400 W/cm² on a warped silicon die
NovoLINC's MaxLINC test held a production-representative silicon die at 400 W/cm² and 3,300 W total power while junction temperature stayed below 90°C.
Kioxia CM9-R E3.S: read ceiling, thin write proof
The endurance line, not the read ceiling, sets the tone for Kioxia's CM9-R E3.S: 1 DWPD, PCIe 5.0, NVMe 2.0, and up to 3,400K random reads with 540K random writes.
Colorful's 32GB CL30 kit prices latency in China
Colorful lists a 32GB iGame Shadow II DDR5-6000 CL30 kit in China at 3,999 yuan, with two 16GB DIMMs and a 500-yuan premium over CL36.
Tesla AI5 memory set at 96GB to share the minimum LP5 tier
Tesla's AI5 chip carries 96GB of LP5 DDR5, up from a 72GB floor, so the company is not the sole buyer of the minimum memory tier.
The 55.8 percent energy saving is a model output
Trace-driven simulations in arXiv:2609.39131 report 36.1 to 87.0 percent completion-time reductions when HBF extends the HBM memory hierarchy for agentic LLM serving.
BiWin CL 100 Mini: 2TB in a 15-by-17 mm footprint
BiWin's CL 100 Mini packs up to 2TB of storage into a 15 x 17 mm board, aimed at portable gaming rigs.
RTX 5070 Ti GDDR7 memory reaches 39 Gbps in an overclock test
A Samsung GDDR7 module on an RTX 5070 Ti reportedly ran at 39 Gbps, or +5500 MHz, while +6000 MHz produced artifacts or crashes.
Hamamatsu's iPHEMOS-DDX packs seven FA techniques into one inverted stage
Hamamatsu Photonics K.K. filed a press release on October 1, 2026, introducing the iPHEMOS-DDX, an inverted emission microscope integrating seven failure-analysis techniques for AI chiplets and HBM packages.
Cervoz T449 and T459 leave endurance unmeasured
Cervoz lists the T449 and T459 as M.2 2280 NVMe drives with PCIe Gen4 x4, 5,085 MB/s read, and 4,765 MB/s write.
86.25 percent gross margin, $53 billion profit, and a 2028 shortage
Micron's quarterly filing pairs a record 86.25 percent gross margin with over $53 billion in profit and a shortage projection running through 2028.
Infineon's Bangkok backend site leaves the numbers buyers need unprinted
Infineon's new Bangkok backend site starts at 350 staff and scales to five modules, but the release prints no wafer size, no capex, and no ramp date.
Micron 2027 output 75% committed; customer talks shift to 2028
Micron's Q4 FY26 filing puts more than 75% of 2027 output under contract, pushing most customer negotiations into 2028.
Montage's CK01P and RCD05 enter mass production at 9200 and 8000 MT/s
Montage Technology's CK01P CKD hits 9200 MT/s on mainstream DDR5 and the RCD05 pushes RDIMMs to 8000 MT/s, both now in mass production.
US datacenter buildout meets a packaging ceiling
SynMax estimates US datacenter gross capacity will rise from about 11 GW in 2025 to 16-18 GW in 2026, with 2027 capped in the low 20s.
One DDR4 stick died in 90 minutes under a 35B LLM, and nobody measured the DIMM temp
One 8GB DDR4 ECC module failed 90 minutes into a 35B LLM inference run, and the user never recorded a DIMM temperature.
Virginia Tech liquid metal composite reports 40x thermal conductivity
The Virginia Tech composite stretches gallium-indium droplets inside soft silicone and reports a 40x thermal conductivity boost in a printed material.
GPUThor breaks the ECC safety assumption on NVIDIA GPUs
University of Toronto researchers demonstrated a rowhammer attack that defeats ECC protection on NVIDIA GPUs by exploiting non-uniform hammering patterns across refresh intervals.
Micron's GDDR7 2 GB chips hit EOL after just months of RTX 50 supply
Micron's 2 GB GDDR7 chips at 28 and 32 Gbps reached end-of-life status on the company's product page, ending a supply window that lasted roughly two months.
AMD Lays GDDR7 Groundwork in the Linux Kernel for RDNA 5
AMDGPU patches add a GDDR7 identifier and new IP blocks, signaling RDNA 5 may finally move off aging GDDR6.
DRAM die value per area now exceeds TSMC N3 compute silicon
AI-driven demand has pushed DRAM die value per square millimeter past what TSMC charges for its N3 compute wafers, per Tom's Hardware.
Concurrent HBM and host memory access lifts LLM inference throughput by 31 percent
BOOST, a runtime system from Georgia Tech, Nvidia, and Stanford, improves LLM inference throughput by 31 percent on Grace Hopper by concurrently accessing HBM and host DRAM.
Onsemi's EPP platform uses silicon wafer for 5x power density
Onsemi's EPP platform replaces traditional PCB substrates with silicon wafers, promising up to 5x power density for AI chips and EVs.
Intel and AU Optronics Collaborate on Advanced Packaging for Micro LED and CPO
Intel is partnering with AU Optronics to develop CPO and high-density chip layouts using Micro LED substrates and glass-based interconnects.
Leaker claims 4 GB and 6 GB GDDR7 chips will roll out in the next two years
Leaker Golden Pig Upgrade says memory makers will roll out 4 GB and 6 GB GDDR7 chips in 2027 or 2028, a big jump from the 2 GB modules the RTX 50 series uses.
Kioxia shows the XL1 CXL XL-FLASH NAND device
Kioxia showed its XL1 CXL XL-FLASH NAND device, a NAND-based memory device that uses CXL, as DRAM supply tightens.
ASUS Prepares BIOS Updates for AM5 Motherboards to Optimize CXMT Memory Latency
ASUS is preparing new BIOS updates for its AM5 motherboards that target CXMT DDR5 memory modules with additional low-latency tuning, based on AMD AGESA ComboAM5 PI 1.3.0.1d.
Predicting thermal conductivity in advanced BEOL interconnect stacks
Peking University researchers published a framework for predicting thermal conductivity in BEOL interconnect stacks in advanced technology nodes, enabled by extensive layer-resolved thermal measurements.
Astera Labs Leo 2 and Leo X target DDR4 reuse in CXL memory expansion
Astera Labs' Leo 2 controllers double CXL bandwidth to PCIe Gen6 speeds and support up to 4TB DDR5 per expander card.
1.6 TB/s and what the Triad number leaves out
AMD's EPYC Venice platform posts 1.6 TB/s sustained memory bandwidth on STREAM Triad, 18% ahead of NVIDIA Vera's 1.2 TB/s LPDDR5x figure.