CXMT says it completed verification of an engineering sample for its 4F²-based 6th-generation DRAM platform, and the page's figure is a captioned photo of CXMT Hefei Plant 1. The caption identifies CXMT Hefei Plant 1, not the wafer, the cell, or the DDR5 RDIMM sample it may send by the end of this year. That gap matters because the article is selling a process step, not a measured product.

The document defines F as the minimum lithography line width and 4F² as one memory unit sized at four times F squared. The current mainstream DRAM structure is 6F², so the claimed step increases transistor count per unit area and memory integration density. The wafer is said to have reached core performance targets, but the article gives no yield, power, speed, or benchmark figure.

Die Brief reads the photo as the concrete part of the page, because it locates the claim in a fab, not in a customer board. The constrained party is CXMT, because customer verification still stands between the engineering sample and mass production, and the statement names no customer, price, benchmark, or fab capacity. The buyer should treat the 4F² claim as a process milestone, not as a shipping DDR5 RDIMM.

What is still unmeasured is whether the 4F² cell survives customer qualification at server scale. Left out are yield, power, latency, price, and the identity of any customer.

The document leaves out yield, power, latency, price, customer names, and fab capacity.

The wafer result is a process milestone, not a product qualification. Customer verification, yield, power, and benchmark data are absent, so the DDR5 RDIMM claim remains unproven.