That is the sustained memory bandwidth AMD reports for the EPYC Venice platform on a STREAM Triad run, against 1.2 TB/s on NVIDIA Vera's LPDDR5x. The number does not prove that the 16-channel, 12,800 MT/s RDIMM design holds under the mixed read-write patterns of agentic inference, where the working set shifts between context windows and tool-call buffers.

The desk reads the 18% delta as a memory-subsystem fact, not a workload fact. A buyer sizing a 100-kilowatt rack for agentic serving is constrained by the gap between a Triad benchmark and sustained model throughput. AMD's whitepaper models 3.4x rack-level throughput versus Vera but does not publish per-node power draw or the thermal envelope at which that model holds. The supply-chain-transparency filing, the document this page is keyed to, contains no performance data at all.

What remains unmeasured: per-core latency under concurrent agentic tool-calls, thermal headroom at 96 cores under sustained load, and whether the 8% per-core bandwidth advantage survives on a full 256-core socket rather than the 96-core test chip.

The 18% bandwidth delta is a memory-subsystem measurement, not a workload result, and it does not close the gap between a Triad run and sustained agentic model serving. The supply-chain-transparency filing contains no performance data; the 3.4x rack-level figure is modeled, not measured.

The supply-chain-transparency filing contains no performance, power, or thermal data of any kind.

The STREAM Triad number validates the 16-channel, 12,800 MT/s RDIMM path but says nothing about controller contention under concurrent tool-call workloads. The 3.4x rack figure is a model; per-node power and thermal envelope are unpublished.