Samsung's vendor page at media.naver.com/press/015 puts the 12-layer HBM4E sample at a stable 14 Gbps per pin. The same filing lists 48 GB per stack, bandwidth up to 3.6 TB/s, and a scalable ceiling of 16 Gbps. It names 1c DRAM and a 4nm logic base die, with stability tied to HBM4 experience.

Wccftech added that the stack passed NVIDIA qualification, a step the vendor page does not state. That claim moves the story from sample shipment to customer acceptance. The vendor page only says mass production will follow customer schedules.

The useful number is not the qualification rumor but the gap between sample and supply. A buyer cannot price a next-generation GPU from a page that gives no volume, no contract value, and no delivery date. For the fab, the 1c/4nm pairing is the real constraint: it ties memory yield to logic-die capacity and thermal headroom. The 16% energy-efficiency and more-than-14% thermal-resistance figures are design claims, not measured field data.

Capacity is the second lever: 48 GB per stack is more than 30% above the previous generation. That matters when a GPU must hold model weights close to the compute die. The planned 32 GB and 64 GB variants give customers a path, but the vendor page does not assign them to any platform. The page says the samples went to major global customers.

The document leaves out qualification status, mass-production start, and customer allocation. It also does not measure power draw, failure rate, or yield at scale. Until those numbers appear, the 16 Gbps scalable figure remains, for now, a ceiling, not a supply commitment. Even the 3.6 TB/s bandwidth is a per-stack figure, not a system-level throughput number.

The qualification claim is not in the vendor page, so it cannot be treated as a supply decision. The buyer-facing constraint is the missing volume, schedule, and yield data behind the 14-to-16 Gbps sample.

The document leaves out qualification status, mass-production start, customer allocation, power draw, failure rate, and yield at scale.

The vendor page proves sample capability, not qualification, volume, or yield; the 1c/4nm stack and 16% efficiency claim are design targets until system-level power and thermal data appear.