CoWoS capacity, not HBM samples, gates accelerator supply
CoWoS packaging capacity is the limiting step for HBM4E, even though SK hynix and Samsung have shipped 12-layer samples to Nvidia and other customers.
| SK hynix 12-layer HBM4E | Samsung 12-layer HBM4E | |
|---|---|---|
| layers | 12 | 12 |
| speed per pin | up to 16 Gbps | stable 14 Gbps, up to 16 Gbps |
| bandwidth | up to 3.6 TB/s per stack | |
| power efficiency | more than 20 percent from previous generation | |
| sample shipment | to major customers | late May |
The sample shipments reach Nvidia and other major customers for future data-center GPUs such as Rubin Ultra. SK hynix and Samsung have both provided 12-layer HBM4E samples.
SK hynix reports its sample reaches up to 16 Gbps per pin and improves power efficiency by more than 20 percent versus the previous generation. Samsung describes its sample as stable at 14 Gbps per pin, scalable to 16 Gbps, and reaching up to 3.6 TB/s per stack.
The limiting step is TSMC CoWoS packaging capacity, not the memory stack itself. CoWoS packaging capacity, not memory speed, decides whether those samples become accelerator supply.
Qualification hinges on heat dissipation, power efficiency, base-die design, and packaging stability inside the customer's accelerator. CoWoS capacity, yield, and system-level thermal results remain unmeasured.
Pin speed alone does not establish final accelerator supply. The document establishes sample availability, not the packaging allocation that would turn those samples into accelerator supply.
No CoWoS capacity figure, allocation to SK hynix or Samsung, or Rubin Ultra package yield appears in the page.
The brief correctly separates sample specs from packaging capacity, but it should not imply supply is confirmed.
After ajupress.com. We did not report this. The pictures, if any, are theirs.
