Morgan Stanley's CoWoS forecast turns 2026 capacity into a schedule constraint
Second-tier ASIC makers get less than 15% of TSMC's 2026 CoWoS capacity in the Morgan Stanley split.
| NVIDIA | Broadcom | AMD | |
|---|---|---|---|
| 2026 CoWoS wafers | 595,000 | 150,000 | 105,000 |
| share of global demand | 60% | 15% | 11% |
| TSMC wafers (named allocation) | 510,000 | 85,000 | 80,000 |
| OSAT wafers (named allocation) | 80,000 | 5,000 | |
| Google TPU wafers | 90,000 | ||
| Meta wafers | 50,000 | ||
| OpenAI wafers | 10,000 | ||
| Rubin platform shipments | 2.4 million |
NVIDIA's 595,000-wafer 2026 CoWoS demand is 60% of the 1,000,000-wafer global total.
TSMC undertakes about 510,000 of those wafers for Rubin, while OSATs such as Amkor and ASE/SPIL undertake about 80,000 for Vera CPU and automotive chips.
Broadcom's 150,000-wafer allocation includes 90,000 for Google's TPU, 50,000 for Meta, and 10,000 for OpenAI.
AMD's 105,000-wafer allocation includes 80,000 at TSMC for MI355 and MI400 accelerators.
Amazon reserves 50,000 wafers through Alchip, Marvell reserves 55,000 for AWS and Microsoft, and MediaTek reserves 20,000 for Google's TPU.
The named customers lock more than 85% of TSMC's CoWoS capacity, so the scarce resource is schedule, not silicon.
Scheduling is generally postponed to 2026 or later, so a 2026 design without a reserved wafer slot becomes a 2027 design.
Yield, defect rate, HBM stack availability, and actual 2026 output remain unmeasured.
Intel EMIB and Samsung 3.3D are unmeasured as overflow options, and the 15% residual is still unassigned.
The allocation is a schedule constraint, not a demand proof.
After mp.weixin.qq.com. We did not report this. The pictures, if any, are theirs.
