Onsemi's EPP platform uses silicon wafer for 5x power density
Onsemi's EPP platform replaces traditional PCB substrates with silicon wafers, promising up to 5x power density for AI chips and EVs.

Onsemi's Embedded Power Platform (EPP) replaces the conventional PCB substrate with a 12-inch silicon wafer, claiming up to 5x power density for AI chips and EVs. The platform is a single-source announcement with no SKU sheet, and the 5x figure is an application-dependent ceiling. Onsemi is taking a different approach than Intel's EMIB, which routes power around the embedded package, and EMIB-T, which routes power through the embedded die.
EPP embeds FETs, drivers, and controllers directly in the silicon wafer and co-optimizes them for electrical, thermal, and mechanical performance. It integrates silicon, silicon carbide (SiC), and gallium nitride (GaN) in a single package. The shorter connections from chip to base board cut parasitic inductance, which reduces power losses from current flow and voltage fluctuation, and enables higher switching frequencies. The wafer itself conducts heat, which improves thermal management over a conventional PCB.

What changed versus the status quo is the package's role. Traditional packages are passive housing; EPP makes the package an active contributor to system performance. For EV traction inverters, the platform claims up to 4x higher power density and 15% lower power losses, enabling smaller, lighter inverter designs. A single inverter platform can span low-end to high-end vehicle applications, letting automakers reuse a common design across models and power classes, which reduces R&D and manufacturing costs and accelerates qualification cycles. For AI infrastructure, an early EPP-based solid-state circuit breaker was ~50% smaller and 20% cooler than existing designs, freeing rack space and cooling capacity for compute.
The production timeline and the partner list beyond Subaru. Onsemi has named Subaru as an early partner for EV applications, with engineering samples and simulation models to follow. Wider sampling to key customers is expected later this year, but no data-center customer is named, and no yield or cost figures are given. The 3-5x density range and the 4-month development-cycle claim are Onsemi's, not independently measured. The development-cycle reduction to four months is a process claim, not a measured result.
The sampling round and whether a data-center customer appears. The solid-state circuit breaker is the near-term AI-infrastructure application, and the EV inverter platform is the one with a named partner. A second customer or a yield figure would move this from SINGLE-SOURCE toward CONFIRMED. The 12-inch wafer choice is the part that distinguishes EPP from the EMIB family, and it is the part most likely to be validated in the sampling round. The switching-frequency gain is the number that matters for the EV inverter, and it is the one most likely to be measured in the engineering samples.
Onsemi's EPP leverages advanced packaging to enhance power efficiency and density. While promising, its widespread adoption hinges on cost and manufacturing feasibility.
Up to 5x power density gain · Reduces development complexity · Enables faster time-to-market · Improves thermal performance
After Wccftech Hardware. We did not report this. The pictures, if any, are theirs.

