Groq's next LPU swaps SRAM for 3D stacked DRAM
The next Groq LPU reportedly swaps 500 MB of SRAM for 3D stacked DRAM, raising capacity while leaving bandwidth unmeasured.
| Groq LPU | next-generation chips | |
|---|---|---|
| memory | 500 MB SRAM | 3DS DRAM |
| bandwidth | 150 TB/s | |
| compute | 1.20 PFLOPs FP8 | |
| rack chips | 256 | |
| rack SRAM | 128 GB | |
| scale-up bandwidth | 640 TB/s | |
| tokens/s with NVL72 | 3,400 | |
| production | August |
DRAM layers would connect through TSVs in the next Groq LPU, moving away from the existing SRAM design. A ZDNet Korea report, citing a semiconductor insider, says Groq is weighing 3D stacked DRAM, or 3DS, for next-generation chips. The current LPU figure is 500 MB of SRAM.
DRAM offers higher capacity but trades off bandwidth. The LPX rack is the measured baseline: 256 chips, about 128 GB of SRAM, 640 TB/s of scale-up bandwidth, and 1.20 PFLOPs FP8 per LPU. The pressure is model size, not token speed.
A buyer can expect more capacity, but a fab or integrator cannot price the part until the DRAM stack's bandwidth and power are measured. Next-gen DRAM capacity, bandwidth, compute, rack configuration, power, and SKU name remain unmeasured.
Capacity is the change; bandwidth is the open variable.
After zdnet.co.kr. We did not report this. The pictures, if any, are theirs.
