The stack tested was two layers of LPDDR5X DRAM with a small compute unit mounted beneath the dies. Qualcomm's production target is four layers.

The measured bandwidth sits at 18× external LPDDR5X, though no absolute gigabyte-per-second figure was disclosed. The 5× and 18× multipliers are relative to baselines Qualcomm did not publish.

The constraint is thermal, not electrical. A compute die buried under two or four DRAM layers has no airflow path, and while the validation included heat-development tests, Qualcomm published nothing on the results.

That missed 6× target means the thermal headroom the architecture was supposed to buy is thinner than planned.

The substrate claim is the real cost lever. If less interconnect bandwidth is needed between the compute unit and the SoC, organic 2D substrates could replace advanced packaging. That would reshape the cost structure, but only if TSV yield holds at four layers, and the document does not prove it.

Absolute bandwidth in GB/s, stack capacity in gigabytes, power draw in watts, and the thermal data from the validation are all absent from the release.

The Dragonfly AI250 accelerator, slated for sampling in the first half of 2027, is the first product to ship with HBC.

The draft repeated the thermal/substrate paragraph nearly verbatim and buried the missed-target angle in the middle. The rewrite leads with the gap between 5× and 6×, front-loads the architecture in one short beat, and treats the missing absolute figures as a closing caveat rather than a mid-piece interjection. Rhythm shifts from four long paragraphs to seven shorter ones, and the lede now names the shortfall instead of the validation event.