Zen 6's 27 percent IPC compares two chiplets, not one core
The 27 percent IPC number AMD attaches to Zen 6 comes from pitting 16 Zen 6c cores on one chiplet against 16 Zen 5 cores on two chiplets at the same clock.
| Zen 6 | Zen 6c | |
|---|---|---|
| cores per CCD | 12 | 32 |
| L3 cache | 48 MB | 128 MB |
| L3 per core | 4 MB | 4 MB |
| L2 per core | 1 MB | 1 MB |
| reorder buffer | 640 entries | 640 entries |
| delivery bandwidth | 18 ops/cycle | 18 ops/cycle |
That setup bundles a fourfold L3 jump per core, from 2 MB to 4 MB, with a 640-entry reorder buffer and an 18-operations-per-cycle delivery path. A single-core test would not surface any of it.
AMD's own framing splits the delta: roughly 20 percent in enterprise and cloud workloads, 31 percent in AI. The four VNNI-INT8 pipelines and Bit Matrix Multiply instructions carry the AI number; the cache-per-core increase carries the cloud number.
No process node, no TDP, no die size, and no Ryzen desktop SKU or release date appear in the disclosure. The 5.3 GHz ceiling and the 16-channel SP7 platform belong to the EPYC Venice server socket, not a desktop board.
The 27 percent figure is structurally a multi-CCD comparison that conflates cache and pipeline gains, and AMD's own 20/31 split confirms the delta is workload-dependent rather than a flat per-core number. The absence of node, TDP, and die-size data means a fab buyer cannot price the silicon from this disclosure alone.
After amazon.com. We did not report this. The pictures, if any, are theirs.
