The EPYC Embedded 9006 Series SP7, filed on 10 November 2026, carries no unit price on the Phoronix page. Neither figure is a measurement. The 600-watt TDP is a thermal design ceiling, and the 4.1 GHz is a maximum frequency, not a sustained clock under load. The Phoronix page is the only document in the packet that names a figure for either end of the stack.

Between those two endpoints sit four more parts: the 192-core EPYC 9946, the 168-core EPYC 9846, the 128-core EPYC 9756, and the 96-core EPYC 9656. All six SKUs run on Zen 6 and share a 16-channel DDR5 memory controller that accepts RDIMM or MRDIMM modules. The document does not state a memory speed in MT/s, a maximum capacity per channel, or a minimum DIMM configuration. The 16-channel figure is the same across the entire stack, which means the 64-core part and the 256-core part see the same memory bandwidth ceiling. A buyer who drops from the 9976 to the 9556 does not lose a channel, but the 64-core part will not saturate those 16 channels the way the 256-core part will.

The interconnect is uniform. Every part in the EPYC Embedded 9006 series exposes 96 lanes of PCIe Gen 6 and CXL 3.1. AMD does not publish a CXL lane count or a bandwidth figure for the 3.1 implementation. No figure in the document tells whether those 96 lanes are split between PCIe and CXL, whether CXL borrows from the same pool, or whether the 96 is a PCIe-only number with CXL as an additional allocation on top. The PCIe Gen 6 designation doubles the per-lane bandwidth of Gen 5, which matters for an embedded buyer routing NVMe or accelerator traffic through the same socket, but the document does not state a per-lane transfer rate or a total aggregate bandwidth.

AMD's promotional multiplier is 1.8x socket throughput over the prior-generation EPYC Embedded 9005 series, and 2x performance over Intel Xeon 6 processors. Both numbers are AMD's framing, stated in the same breath as the spec sheet. Phoronix had no hardware in the lab at the time of filing, and no independent measurement appears anywhere in the document. The 1.8x figure is a theoretical peak relative to a specific prior-generation configuration, not a sustained-load measurement, and the 2x figure does not name which Xeon 6 SKU or which workload produced it. A buyer who needs a number to put in a BOM should treat both multipliers as marketing until a lab publishes a measurement.

The seven-year longevity guarantee covers CPU availability, long-term firmware support, security support, and drop-in next-generation processor compatibility. For an embedded buyer designing a chassis that will sit in a factory, a rail car, or a defense installation for a decade, that guarantee is the part of the spec sheet that outlives the silicon. The guarantee does not cover board-level support, OS-level patches beyond AMD's control, or the cost of the next-generation drop-in part. It is a supply-chain promise, not a performance guarantee, and it does not state what happens if the 9976 is superseded by a part with a different socket.

The non-embedded EPYC 9006 SP7 lineup, which includes the 256-core EPYC 9996 and the 96-core 5.3 GHz EPYC 9686F, was announced the same day and is a separate product with its own thermal and socket envelope.

The absence of pricing is not an editorial gap in the filing. AMD did not name a single SKU price, a per-core rate, or a volume tier during the launch briefing. The number has to come from a board partner, and the document does not name one. The embedded channel has always priced through the system integrator, but the 600-watt flagship changes the arithmetic for anyone who was running a 9005-series part at a lower TDP and now has to re-engineer the cooling path, the power delivery, and the chassis airflow. The 64-core 9556 at a lower TDP is the part that fits in the existing chassis; the 9976 is the part that requires a new chassis, a new power supply, and a new thermal design.

The constraint is not the silicon. It is the integrator who must size a cooling envelope for 600 watts in a chassis that was not designed for a server-class part, and who must accept a CXL 3.1 interface whose lane allocation is not published. The 1.8x and 2x multipliers are AMD's promotional framing, not a measurement from any lab in this packet, and the document does not prove them. What the buyer still cannot know is whether the 4.1 GHz maximum frequency on the 9976 is achievable at the full 600-watt ceiling or whether it requires a lower core-activation state, and whether the 16-channel memory controller on the 64-core part delivers the same bandwidth as the 256-core part under a full-channel load. The document does not answer either question.

What is still unmeasured: no benchmark, no memory speed in MT/s, no socket designation, no board partner name, and no price. The 600-watt figure is a TDP ceiling, not a sustained-load number, and the CXL 3.1 lane count is not broken out from the 96 PCIe Gen 6 lanes. The document is a spec sheet, not a measurement, and the next filing will be the one that puts a number on the 9976 under load.

The constraint is the integrator who must size a 600-watt cooling envelope in a chassis not designed for server-class parts while accepting a CXL 3.1 interface whose lane allocation is unpublished. The 1.8x and 2x multipliers are AMD's promotional framing, not a measurement, and the document does not prove them.

No benchmark, no memory speed in MT/s, no socket designation, no board partner name, no CXL lane count, and no unit price appear in the document.

The EPYC Embedded 9006 SP7 is a Zen 6 embedded platform with a six-SKU stack from 64 to 256 cores, 16-channel DDR5, 96 PCIe Gen 6 lanes, and CXL 3.1. The 600-watt TDP on the 9976, the absence of pricing, memory speed, socket designation, and CXL lane count leave the buyer without the numbers needed for a BOM or a thermal design.