Venice-X drops V-Cache below the CCD and lifts the Epyc ceiling to 5.3 GHz
The V-Cache moves from the top of the CCD to the bottom, and AMD's Epyc 9006 Venice clock ceiling goes from 3.7 GHz to 5.3 GHz as a result.
| Venice-X | |
|---|---|
| cores | 96 (8 × 12) |
| max clock | 5.3 GHz |
| socket | SP7 |
| V-Cache position | under CCD |
| ship window | 2nd half 2027 |
AMD showed this at the In Depth 2026 NDA event in Las Vegas. The maximum configuration is 96 Zen-6 cores in the SP7 socket, shipping in the second half of 2027.
The old top-mounted stack acted as what AMD called a warming blanket, trapping heat between the CCD and the heatspreader. Below the die, the thermal path shortens, and the 1.6 GHz gap between the old and new ceiling is the payoff.
The teaser performance slide AMD circulated at the session is still Milan-X (Epyc 9004) data, per the ComputerBase write-up. No Venice-X benchmark exists yet.
No TDP figure, no per-CCD V-Cache capacity, no IPC delta versus Turin, and no confirmed SKU count beyond one, two, or maybe three additional models appear in the preview.
The buyer no longer has to pick between X3D and high-frequency SKUs. The 96-core high-clock parts that were the best sellers before now get the stacked cache without the thermal penalty, but the thermal envelope itself is still unpriced.
The architectural move is confirmed and the 5.3 GHz ceiling is real, but the preview is thin on thermal data. The Milan-X teaser slide is the biggest misreading risk, and the absence of a TDP figure means 5.3 GHz is a ceiling, not a sustained clock. The longer-term story is that X3D and high-frequency SKUs finally coexist, which changes the buyer's trade-off.
After computerbase.de. We did not report this. The pictures, if any, are theirs. Also filed by The Register.
