Epyc 9006 Venice replaces the older interconnect with EFB at 256 cores
AMD's first Zen 6 server chip, the 256-core Epyc 9006 Venice, pairs EFB die-to-die links with a CCD33 layout of 32 active cores plus one redundant per chiplet.
| Zen 6c (CCD33) | Zen 6 (CCD) | |
|---|---|---|
| Cores per CCD | 32 active + 1 redundant | 12 |
| L3 per core | 4 MB | 4 MB |
| L3 total per CCD | 128 MB | 48 MB |
| FP-Scheduler entries | 60 each | 46 each |
| L3 misses to memory | 1,280 | 480 |
| Process | TSMC N2 |
203 billion transistors sit on TSMC N2 in the Venice die. The CCD33 arrangement gives each chiplet 32 working cores and one spare, with 128 MB of L3 cache per CCD.
The 27 percent IPC gain AMD printed in Las Vegas compares 16 Zen 6c cores packed into a single CCD against 16 Zen 5 cores spread across two CCDs. No buyer will populate that configuration, so the number does not map to a like-for-like upgrade.
Memory bandwidth, not IPC, is the binding constraint at 256 cores. Each CCD tracks 1,280 outstanding L3 misses, and the EFB link's latency to the IOD is not stated anywhere in the document.
No clock speed, TDP, price, socket pin count, or PCIe lane number appears in the material. The 27 percent figure is a vendor keynote measurement, not an independent lab result.
The EFB swap is the structural story here, but the 27 percent IPC number is a vendor-selected comparison that no independent lab has replicated. The CCD33's 1,280 outstanding L3 misses make memory bandwidth, not IPC, the real ceiling at 256 cores, and the EFB-to-IOD latency gap means the scaling curve from 128 to 256 cores remains AMD's projection rather than a fab-verified result.
After computerbase.de. We did not report this. The pictures, if any, are theirs. Also filed by ComputerBase, ServeTheHome.
