Tesla's AI5 chip is now specified with 96GB of LPDDR5, after an earlier statement placed it at 72GB. The Wccftech filing says the 96GB setting sits above the minimum LP5 configuration, not inside it, because Tesla would otherwise be the only buyer on that minimum. The chip is tied to Optimus and was said to have taped out in April. The earlier cut had been framed as a response to a global memory shortage.

The constraint is memory supply, not silicon. The document does not prove that 96GB is enough for Optimus workloads, nor that the higher capacity per chip is affordable at scale. For a fab or DRAM buyer, the move raises the per-unit memory attach and weakens the earlier half-cut story. It also shifts the negotiation point from raw core count to the amount of LPDDR5 each robot board must carry.

What is still unmeasured is the actual DRAM allocation per AI5 board, the power draw of the 96GB package, and whether the claimed Hopper or Blackwell comparisons hold. The page names the capacity change, but it leaves the supply curve and the performance test absent. No board-level bill of materials, node, or watt figure appears in the page. A later correction can therefore be expected if the 96GB figure is a package option rather than a fixed robot configuration.

The constraint is memory supply, not silicon. The higher LPDDR5 attach raises the DRAM bill and weakens the earlier half-cut story.

The document leaves out board-level DRAM allocation, power draw, and performance test results.

The 96GB LPDDR5 choice is a supply-side correction, not a performance proof. It increases DRAM per AI5 board and makes the earlier 72GB cut less meaningful for procurement.