AMD does not price the MI430X on its own product page. The chip is named, positioned, and linked to a "Learn More" page that contains no additional figures. The MI430X is the second GPU in the MI400 Series, designed for sovereign AI and HPC, and the document's entire specification for it is a single sentence: it combines FP64 accuracy for simulation and modeling with modern AI capability for inference, training, and fine-tuning. The page is the MI400 Series overview, not a dedicated MI430X spec sheet, and the chip appears in a section roughly one-third the length of the MI455X section.

The configuration the starting price buys is, in the document's terms, undefined. There is no price, no memory capacity, no bandwidth figure, no FLOPS number in any precision, no TDP, no process node, no package type, and no launch date. The page links to "Learn More" beneath the MI430X description, but the deeper page in the packet does not add a single figure for this chip. The buyer who arrives looking for a spec sheet finds a market segment, a software stack, and a case study. The starting price configuration is not a configuration at all; it is a placeholder for a product that AMD has not yet specified publicly.

The headline number on the page is 2.9 exaFLOPS peak OCP MXFP4. That number belongs to the AMD Helios rackscale solution, which is powered by 72 MI455X GPUs. It is not a number for the MI430X. No peak FLOPS figure is assigned to the MI430X in any precision. The MI430X has no headline number in this document. The stretch between the two configurations is not a tier difference in the usual sense; it is the difference between a specified product and an unspecified one.

The 2.9 exaFLOPS figure is a peak, and the document labels it OCP MXFP4. OCP MXFP4 is a 4-bit floating-point format from the Open Compute Project. The CDNA architecture section on the same page states support for "OCP MXFP 8/6/4 (including INT8, and FP16/BF16 sparsity support for AI)." The page does not explicitly state whether the 2.9 exaFLOPS peak assumes sparsity, but the architecture description makes sparsity a supported mode of the CDNA matrix cores. The peak is theoretical. The document separately lists 1.67 PB/s of memory bandwidth and 1.7 PB/s Peak Theoretical Memory Bandwidth for the Helios rack, which distinguishes a sustained figure from a theoretical ceiling. The 2.9 exaFLOPS sits in the same category as the 1.7 PB/s: a peak, not a measurement. A buyer who needs a sustained throughput number for a procurement model will not find one on this page.

The Helios rack configuration, which the headline number describes, carries 31 TB of HBM4 memory, 1.67 PB/s of memory bandwidth, and up to 260 TB/s of scale-up bandwidth per GPU. The rack combines 72 GPUs with AMD EPYC server CPUs and AMD Pensando networking. The document calls it a "fully integrated AI infrastructure" designed using open industry standards, enabling large-scale inference, frontier model training, and fine-tuning. The MI455X, the GPU that powers this rack, carries 432 GB of HBM4 across 12 stacks, 23.3 TB/s of bandwidth, 40 PFLOPS FP4, and 20 PFLOPS FP8/FP6 on a CoWoS-L package with 3D hybrid bonded compute dies.

The MI430X shares the CDNA architecture and the ROCm software stack with the rest of the MI400 Series, but the document provides no comparable hardware figures for it. The tier split is explicit: frontier AI gets the Helios rack, sovereign AI and HPC get the MI430X. The word "sovereign" appears twice on the page. The IBM Sovereign Core case study is linked from the MI430X section, dated October 15, 2026. The document states that ROCm software enables "predictable distributed execution with communication primitives (RCCL), KV-cache optimizations, and compute/communication overlap tuned for exaFLOP-class scale," and that it helps customers "maintain portability across the AMD Helios rackscale solution with AMD Instinct MI455X and MI430X GPUs." The software story is the same for both chips. The hardware story is not.

The document positions the MI430X as the chip for jurisdictions that need FP64 accuracy for simulation and modeling alongside AI workloads. The FP64 capability is the differentiator the page names. to the most demanding FP64 for HPC." The MI430X carries the FP64 end of that range into a sovereign deployment. No FP64 throughput figure is stated for the MI430X, and the page does not say whether it matches the rack GPU in that precision. The HPC buyer who needs a double-precision FLOPS number to compare against a competitor's offering will not find one here.

The desk's judgment: AMD has launched a chip into a market where the buyer's primary constraint is data residency and compliance, not raw throughput. The sovereign AI buyer does not need the highest FLOPS number; they need a chip that runs inside their jurisdiction with FP64 accuracy for simulation workloads and a software stack that does not require a proprietary interconnect. The document proves the chip targets that market and that it runs on ROCm with open standards. It does not prove the chip can deliver on it. Without memory capacity, bandwidth, or a price, the buyer cannot model a deployment, cannot compare the MI430X to a competitor's sovereign offering, and cannot calculate a cost per simulation hour. The process node and package type for the MI430X are not stated; the page says only that it is built on CDNA architecture.

What is still unmeasured: memory capacity, memory bandwidth, FLOPS in any precision, TDP, process node, package type, price, and launch date for the MI430X. The document names the chip and its market. It does not name its numbers.

AMD has shipped a launch page for a chip it has not specified, which means the sovereign AI buyer cannot model a deployment or compare the MI430X against any competitor's offering. The document proves the market and the software stack; it does not prove the hardware.

Memory capacity, memory bandwidth, FLOPS in any precision, TDP, process node, package type, price, and launch date for the MI430X are absent from every page in the packet.

The MI430X page contains zero hardware figures: no memory, no bandwidth, no FLOPS, no TDP, no process node, no package, no price. The only architectural claim is CDNA and FP64 support. Until AMD publishes a spec sheet, the MI430X is a market position, not a product.