The MI455X carries 432 GB of HBM4 across 12 stacks, with a peak theoretical memory bandwidth of 23.3 TB/s. That figure comes from AMD's product page for the Instinct MI400 series, which lists the MI455X as the GPU for the Helios rackscale solution and the MI430X as the GPU for sovereign AI and HPC. The page does not list a price for either configuration.

The 40 PFLOPS FP4 peak sits next to a 35 PFLOPS OCP MXFP4 figure on the same comparison table. AMD labels them as separate rows, which means the 40 PFLOPS number is not the OCP MXFP4 number. The vendor page does not state whether the 40 PFLOPS FP4 figure assumes sparsity. The CDNA section mentions "FP16/BF16 sparsity support for AI" but does not attach a sparsity multiplier to the FP4 peak. The peak is labeled FP4, full stop, on the table.

The MI455X is the GPU that goes into the Helios rack. Seventy-two of them, the page says, produce up to 2.9 exaFLOPS OCP MXFP4 and 1.4 exaFLOPS OCP MXFP8 at the rack level, with 31 TB of HBM4 and 1.67 PB/s of memory bandwidth. The MI430X is the other GPU in the MI400 series, aimed at sovereign AI and HPC, and the page does not give it a memory figure, a FLOPS figure, or a bandwidth figure. The stretch between the two is the difference between a card for a national lab and a rack for a hyperscaler, but the page only quantifies one end of that range.

The chiplet design uses stacked 3D hybrid bonded compute dies on a CoWoS-L package, with AMD Infinity Fabric interconnect tying the dies together. The page says this architecture optimizes compute, memory, cache, and I/O functions independently for performance, power, and manufacturing enhancements. That is a packaging claim. The page does not state the die count, the inter-die bandwidth, or the package dimensions.

The CRN article from the launch event reported a memory bandwidth of 19.6 TB/s for the MI400 series and a rack-level bandwidth of 1.4 PB/s. The vendor page says 23.3 TB/s per GPU and 1.67 PB/s at the rack. The gap is not a rounding difference. The CRN figure for the GPU is roughly 16 percent lower than the vendor page figure, and the rack figure is the same proportion lower. The vendor page is the document that names the configuration and the peak qualifier, so its numbers are the ones that stand. The CRN figure may reflect an earlier revision of the spec or a different measurement basis, but the page does not say which.

The buyer who needs the MI455X is constrained by the rack. The GPU does not appear on the page as a standalone product with a price and a socket. It is tied to the Helios solution, which means the buyer is purchasing 72 GPUs, EPYC CPUs, and Pensando networking as a unit. The MI430X is the only GPU in the series that the page presents without a rack dependency, but it carries no performance figures here. The buyer who wants the 432 GB of HBM4 and the 23.3 TB/s bandwidth is buying a rack, not a card, and the page does not say what that rack costs.

What the page does not prove is whether the 23.3 TB/s bandwidth is achievable across all 12 stacks simultaneously under sustained load. The page calls it peak theoretical, which is the standard qualifier, but it does not provide a measured figure. The 40 PFLOPS FP4 peak is also theoretical. No benchmark, no sustained throughput, no power figure for the GPU alone appears on the page. The 256 WGP count and the Wave32 execution model are architectural facts, not performance measurements.

The Vera Rubin comparison on the same page shows 288 GB of memory and 22.0 TB/s of bandwidth. The MI455X leads by 44 GB of memory and 1.3 TB/s of bandwidth. In FP4, the MI455X shows 40 PFLOPS against 35 for Vera Rubin. In FP8/FP6 Tensor, 20 against 18. In FP16/BF16 Matrix, 5 against 4. The page labels all of these as peak PFLOPS, not measured throughput, and the comparison is AMD's own table, not an independent benchmark.

The scale-up bandwidth figure of 3.6 TB/s per GPU on the MI455X spec section is the per-GPU number. The rack-level figure of 260 TB/s is the aggregate across the 72-GPU Helios configuration. The page does not explain the arithmetic between the two. Three point six terabytes per second times 72 does not equal 260 terabytes per second, which suggests the rack-level figure includes inter-GPU links that are not captured in the per-GPU spec, or that the per-GPU figure is a subset of the total. The page does not resolve this.

What is still unmeasured: the power draw of the MI455X, the sustained memory bandwidth under a real workload, the actual FP4 throughput at the rack level, and the price of any configuration. The page names the architecture, the memory, the peak FLOPS, and the package. It does not name a wattage, a price, or a ship date beyond the 2026 window implied by the launch event. The buyer who needs a number to put in a procurement document will have to wait for a document that is not this one.

The MI455X is not a product you can buy; it is a component in a rack that AMD has not priced. The buyer who needs 432 GB of HBM4 and 23.3 TB/s of bandwidth is purchasing a 72-GPU Helios system, and the page does not say what that system costs or when it ships.

The page does not state the MI455X power draw, a sustained memory bandwidth figure, a measured FLOPS figure, a price, or a specific ship date.

The MI455X spec is a peak-theoretical sheet. No measured bandwidth, no measured FLOPS, no power figure, no price. The 23.3 TB/s and 40 PFLOPS FP4 are architectural ceilings, not sustained throughput. The rack-level 260 TB/s scale-up bandwidth does not reconcile arithmetically with the 3.6 TB/s per-GPU figure, which means the interconnect topology is not fully specified. The buyer is constrained to the Helios rack as the only delivery vehicle for the MI455X, and the MI430X, the only GPU presented without a rack dependency, carries no performance data on this page.