The QSCompute vendor page puts HBM4 at a 2048-bit interface and about 1.6 TB/s per stack. The list also carries 48–64 GB for 16-hi stacks and dates the first mainstream use to 2026. The page names Rubin and MI400 as the platforms that inherit the wider bus. The table also keeps HBM3e at 1024-bit and about 1.2 TB/s, which makes the width jump the visible step.

The Barrack filing adds no separate number to this page. The other desk leaves the allocation point unmeasured, so the useful delta is procurement, not architecture. That matters because the QSCompute text says HBM lead times set accelerator delivery. The text treats allocation as the procurement gate, not a footnote.

The document does not prove that Rubin or MI400 will ship with the same stack count, power draw, or controller behavior. The figure gives a per-stack ceiling, not a system total. A buyer should treat the 1.6 TB/s figure as a stack-level number until the vendor publishes stack count and die-to-die overhead. The base-die logic option is not separated from the DRAM stack itself.

The constrained party is the accelerator maker, not the memory vendor. SK Hynix is listed as mass-producing HBM4, while Samsung and Micron are still ramping. The asymmetry gives Hynix weight over launch timing, and it makes allocation the real spec sheet. For the fab, the custom base-die option shifts some design risk toward the customer.

What remains unmeasured is the actual tokens-per-second gain, the power per byte, and the yield of 16-hi stacks. The source also leaves out base-die cost, controller latency, and whether the 2048-bit interface survives in final silicon. Those gaps decide whether the roadmap becomes a purchase. No number in the page converts the roadmap into a price or a delivery date.

The document proves a stack-level interface change, not a system-level delivery. The buyer is constrained by allocation, while the fab is exposed to base-die design risk.

The page leaves out system bandwidth, power per byte, stack count, controller latency, and delivery dates.

The 2048-bit HBM4 stack raises per-stack bandwidth, but the page does not show stack count, power, or controller overhead. Allocation and base-die ownership are the real constraints for Rubin and MI400.