A rumored Intel Nova Lake table lists three BFC chips, the largest carrying 28 cores and 144 MB of L3 cache under the name Core Ultra 9 4970K BFC. The table appears in a Tom's Hardware report that carries no die shot, no process node, and no TDP figure. The three parts share a single "BFC" designation, which the page does not expand.

The 144 MB L3 at 28 cores works out to roughly 5 MB per core. That ratio is the only architectural signal in the document. It does not prove the process node, the clock, or the die area. A 144 MB L3 on a 3 nm node is a different constraint than the same figure on a 7 nm node, and the table gives no node. The buyer cannot size a socket or a cooler from this table alone. The fab cannot confirm a yield path. What the document does prove is that Intel is planning a 28-core part with a cache large enough to change the memory hierarchy, but the mechanism behind that cache is not stated.

No benchmark, no die shot, no TDP, and no release date appear in the page. The three BFC chips are named but not measured. The 144 MB figure is a ceiling, not a confirmed allocation. Until a node and a clock are printed, the table remains a planning document rather than a product spec.

The 144 MB L3 at 28 cores is the only architectural signal in the document, and it cannot be validated without a process node. The table constrains the buyer's socket and cooler planning but does not prove a yield path for the fab.

The 5 MB-per-core L3 ratio is the sole measurable figure. Without a node, clock, or TDP, the table is a planning artifact, not a product spec. The architectural consequence is a larger memory hierarchy, but the mechanism is unstated.