That is the top-line number in a ten-page preprint from Bristol and RAL, submitted to arXiv on 5 March 2026. The paper, NL2GDS, runs a natural-language description of a circuit through a chain of LLM engines, verifies the resulting HDL, and hands it to the OpenLane flow for synthesis and GDSII layout. The target benchmarks are ISCAS'85 and ISCAS'89.

The pipeline is modular: informal intent in, GDSII out. Multiple LLM engines generate candidate HDL, a verification step filters them, and OpenLane handles synthesis through physical design. The authors report up to 36 percent area reduction, 35 percent delay reduction, and 70 percent power savings relative to a baseline they do not fully specify. No process node, no PDK, no absolute microns or nanoseconds appear in the abstract or the metadata.

The "up to" qualifier is doing real work here. ISCAS'85 and ISCAS'89 are combinational and sequential circuits from the mid-1980s and late 1980s, each with a handful of inputs and outputs. A 70 percent power delta on a 1985 benchmark is a large percentage of a small number. The document does not state which LLMs produced the HDL, what the baseline synthesis configuration was, or whether the GDSII passes DRC and timing closure at any particular node.

For a buyer evaluating whether an LLM front-end can replace a human RTL engineer, this paper proves the plumbing works on toy circuits. It does not prove the output is manufacturable, that the HDL survives formal equivalence checking against a reference, or that the area and power figures hold at 7 nm or below. The constraint is not the LLM; it is the benchmark set. ISCAS'89 is a collection of small sequential circuits from 1989. A modern SoC has orders of magnitude more logic, and the error space in natural-language-to-HDL translation grows with it.

What the paper leaves open: no comparison to Synopsys or Cadence flows, no timing-closure data, no formal-verification pass rate, no named LLM or model size. The next useful step is a run on a larger, modern benchmark with absolute PPA numbers and a stated PDK. Until then, the 70 percent figure is a proof of concept, not a spec sheet.

The ISCAS benchmark set is too small and too old to validate an LLM front-end for production ASIC design. The 70 percent power figure is a best-case delta on a 1985 circuit, not a spec-sheet number for any modern node.

ISCAS'89 is a set of small sequential circuits; a modern SoC has orders of magnitude more logic. Without a named PDK, absolute PPA, or formal-verification pass rate, the pipeline is unvalidated beyond toy circuits.