Your Nvidia GPU has 10 to 40 RISC-V cores inside it, and you will never see them. They are not the thing that renders your frames. They are management processors that handle power sequencing, video encode/decode, security verification, and, since 2018, a large portion of what you think of as your graphics driver. Nvidia's VP of Hardware Engineering Frans Sijstermans put the annual shipment at one to two billion of these cores in 2024. You are buying them every time you buy a GPU.

The key one is the GPU System Processor, or GSP. It packs four RV64 cores behind a platform-level interrupt controller and has been executing driver-side work since 2018. The core is NV-RISCV64, an out-of-order RV64I-MSU implementation with bit manipulation, atomics, and SMP support. Each core sits inside a subsystem Nvidia calls Peregrine, which attaches cache, tightly-coupled memory, a DMA engine, and crypto blocks. The result: three times the performance of the old Falcon core at twice the die area. Nvidia has built more than 20 custom ISA extensions, including 64-bit addressing and secure debug. None of it is standard RISC-V.

Before RISC-V, Nvidia ran Falcon, a proprietary 32-bit pipelined core with no data cache. It first appeared around 2005 on the G98 and by 2016 was in more than 15 engines on a single chip. Nvidia estimated roughly three billion Falcons shipped across that decade. The consumer-facing consequence was direct: from September 2014, Maxwell-era GPUs and later required Nvidia-signed firmware to respond, locking Linux users at boot clocks. The RISC-V replacement fixed the 32-bit ceiling and the missing cache, but the signing requirement stayed. Your GPU still will not boot if the on-die ROM detects tampering.

The source is thin on specifics that matter to a buyer. Sijstermans called the one-to-two-billion figure a 'personal, unofficial guesstimate.' Nvidia has not published a per-SKU core count, so you cannot verify whether your card has 10 or 40. The article does not state what measurable performance improvement the GSP delivers beyond the internal 3x-over-Falcon figure. There is no pricing data, no power delta, and no latency number for driver initialization. The rmlsfm.h header lists 32 microcontroller entries, but mapping those to consumer SKUs is not attempted.

Register headers for Rubin, the architecture after Blackwell, already exist in Nvidia's open kernel modules: dev_riscv_pri.h covers rubin/gr100 and rubin/gr102. The 20-plus custom extensions suggest the ISA will keep diverging from upstream RISC-V rather than converging. Watch whether Nvidia exposes any GSP telemetry to users, or whether the next architecture tightens the lock further. The cores are invisible today. They will likely stay that way.

The GSP offloads driver initialization and power management to on-die RISC-V cores, reducing host CPU involvement in GPU bring-up. The 20+ custom extensions make these cores non-portable and effectively a proprietary ISA in RISC-V clothing.