Eight chiplets, two papers, no shared benchmark
Fengshui co-designs 8 chiplets into bespoke accelerators and reports 48.5% energy reduction, but the dossier's deepest pages describe a different paper entirely.
Fengshui builds accelerators from a pool of 8 chiplets and reports 48.5% energy reduction over homogeneous designs across diverse neural networks. The arXiv preprint (2609.10970, submitted 10 September 2026) also claims 97.8% reduction in energy-delay-cost product, with place-and-route validation for physical implementability. The pool includes network switches, processing-in-memory units, and accelerators with diverse microarchitectures.
The NL2GDS pages in this dossier report "up to 36% area reduction" on ISCAS'85 and ISCAS'89 benchmark circuits. That is a layout-generation pipeline for open-source ASIC flows, not a chiplet co-design result. The document that decides the chiplet question is arXiv:2609.10970, and the number that separates it from the NL2GDS work is 8: the size of the chiplet pool that produces the 48.5% figure. Two different problems, two different benchmarks, no shared measurement.
The constraint falls on the buyer who must commit NRE before knowing which accelerators will consume a given chiplet. Fengshui's co-design loop makes a chiplet's value circular: it depends on the accelerators built from it, which depend on the pool. The paper does not prove that 8 chiplets cover a production roadmap; it proves that 8 chiplets cover the test workloads in the paper. For a fab, the place-and-route validation is the only physical anchor, and it is the only number a packaging team can act on.
No node, no TDP per chiplet, no interconnect bandwidth, no yield data. The 48.5% figure is a simulation result on selected neural networks, not a silicon measurement.
The buyer is constrained by the circular dependency: a chiplet's value depends on the accelerators that use it, and those depend on the pool. The document proves 8 chiplets work for the paper's workloads, not for a production roadmap.
No node, no per-chiplet TDP, no interconnect bandwidth, no yield or silicon data.
The co-design loop makes NRE pricing circular until the pool is fixed. Place-and-route validation is the only physical constraint in the paper; everything else is simulation on selected networks.
8 chiplets in pool · 48.5% energy reduction vs homogeneous · 97.8% EDPC reduction · 4.1% gap to unconstrained heterogeneous · 16.8% prefill energy reduction (MoE) · 12.0% energy reduction (edge AV perception)
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