AISIN's STT-MRAM SoC boots in 65.7 ms
A 16nm FinFET die from AISIN keeps its OS and Tiny YOLOv3 weights in on-chip STT-MRAM, eliminating the DRAM bus from the boot path. The kernel is up 65.7 ms after power-on.
| AISIN SoC | |
|---|---|
| Process | 16nm FinFET |
| CPU | Arm Cortex A53 dual-core |
| GPU | Arm Mali-G31 |
| On-chip memory | STT-MRAM |
| Boot time | 65.7 ms |
| Model weight (reduced) | 9.36 MB |
| Model weight (original) | 17.7 MB |
| Weight reduction | 53% |
The part pairs a dual-core Arm Cortex A53 with an Arm Mali-G31. STT-MRAM sits on the same die and carries both the OS image and the model weights, so no external memory is in the boot path.
The filing prints 65.7 ms as the power-on-to-kernel figure. The Register frames that as 38 times faster than external memory would allow, but the 38× ratio is the wire's derived comparison, not a number in the AISIN document.
The on-chip weight storage tops out at 9.36 MB. Tiny YOLOv3 fits; a model needing 17.7 MB does not, even with the hybrid 8-bit/16-bit multiplication scheme. This part serves one model class and stops there.
No inference throughput, no power draw, no production date. The filing does not say what the chip does after the kernel is up.
A filing-level disclosure, not a product launch. The 65.7 ms boot is specific and verifiable against the AISIN PDF, but the 9.36 MB ceiling and the absence of throughput, power, or timeline data make this a proof of concept for STT-MRAM boot rather than a shippable accelerator. The Register's 38× framing is useful context but is not in the primary document.
After aisin.com. We did not report this. The pictures, if any, are theirs.
