That is the power envelope the University of Minnesota team is targeting in their September 2026 arXiv preprint on 3D heterogeneous integration. The problem is not the compute. It is getting that many watts to the die without the pin count becoming the bottleneck. High power densities in stacked chiplet architectures create a power delivery network problem that conventional single-stage delivery cannot solve.

The paper proposes multistage distributed power delivery networks. The mechanism: instead of routing all current through a single set of pins or a monolithic regulator, the PDN is broken into stages, each optimized for a specific segment of the power path. Voltage regulators are placed closer to the load, reducing the current that must traverse long interconnects between stages. This shifts the impedance profile of the network: each stage presents a lower impedance to its local load, reducing IR drop and transient voltage deviation. The trade-off is die area and control complexity against the current density that a single-stage approach would force through interconnects. The paper frames this as a co-optimization problem: performance, thermal, and reliability constraints must be satisfied simultaneously, not sequentially.

The before state is straightforward: as chiplet stacks grow in power draw, the number of power pins required scales with current, and the package substrate or interposer runs out of real estate for those pins. The interposer becomes the bottleneck, not the die. The after state the paper targets is a distributed architecture where local regulation at each stage reduces the current that must cross long interconnects, relaxing the pin count constraint at the package boundary. The source does not quantify the reduction in pin count, the specific power figures achieved, or the thermal headroom gained, so the before/after remains qualitative at this stage. The paper's contribution is methodological rather than empirical, at least in the form presented here.

What the source does not say: no specific power figure beyond "multi-kW," no node or process technology, no specific chiplet configuration, no benchmark results, no comparison against existing PDN approaches, no thermal model or simulation environment. The abstract excerpt is the entirety of the technical content available in this announcement. The full paper on arXiv (2609.24904) presumably contains the methodology and results, but those are not reproduced here.

Watch for the full arXiv paper to land with the actual PDN topology, the regulator placement strategy, and any simulation or measurement data. The University of Minnesota group has a track record in power integrity research, and if the multistage approach holds up under thermal constraints at multi-kW levels, it becomes a reference architecture for anyone designing beyond 1 kW in stacked chiplet configurations. The announcement tags list 2.5D integration and 3D-IC as the target classes, which narrows the scope.

The pin count bottleneck at high power densities makes single-stage PDN infeasible for stacked chiplet architectures. Multistage distributed regulation shifts the impedance profile locally, trading die area for current density at the package boundary.