The Jaykihn filing on X, dated October 29, 2026, puts Razor Lake-S in 2028 and ties it to the LGA 1954 socket that Nova Lake-S debuts on in early 2027. That is the entire hardware claim in the document. The eTeknix piece that carried the tweet adds Griffin Cove as the P-core architecture, replacing Coyote Cove, and notes that the same core is slated for Xeon Coral Rapids; server SKUs get SMT, consumer SKUs do not.

TechPowerUp's forum thread calls the socket continuity confirmed. The leaker's own words say the opposite: "Nothing was said officially," and the eTeknix text hedges with a conditional. Three desks, three different verbs for the same unverified pinout; the word confirmed does a job that no document in this filing performs.

The constraint falls on the board vendor, not the buyer. If LGA 1954 carries two generations, the BIOS roadmap stretches from early 2027 into 2028 on the same pinout, and the fab amortizes socket tooling across a longer window. What the document does not prove is that the pin map is identical; a leaker's compatibility claim is not a datasheet.

No core count, no process node, no TDP, no SKU name, no price. The 12 Xe3P iGPU figure is the only hardware number in the filing, and it arrived by subtraction: Intel moved it from Nova Lake rather than announcing it. Griffin Cove's clock, its die size, and whether the consumer SKU truly drops SMT are all absent.

The laptop variants — Razor Lake-H, HX, AX — are named but carry no figures of their own. The filing is a single tweet plus one secondary article. The 2028 date is a leaker's calendar, not a fab schedule.

The constraint lands on the board vendor: a two-generation LGA 1954 window stretches the BIOS roadmap and amortizes socket tooling, but the pin map itself is unverified. The buyer gains a cheaper upgrade path; the fab gains a longer amortization window, and neither fact is confirmed by Intel.

No core count, process node, TDP, SKU name, or price appears in any document; the 12 Xe3P iGPU figure arrived by subtraction from Nova Lake.

Two-generation socket reuse shifts the BIOS support burden to the board vendor and extends tooling amortization for the fab. The pin map is unverified; a leaker's compatibility claim is not a datasheet, and the buyer's upgrade path depends on a BIOS update that has not been committed.