Razor Lake-S holds LGA 1954 for a second generation without a core count
Intel's Razor Lake-S desktop family targets 2028 on the LGA 1954 socket, with Griffin Cove P-cores and Golden Eagle E-cores, but no core count or TDP has been published.
| Arrow Lake-S | Nova Lake-S | Razor Lake-S | |
|---|---|---|---|
| Core series | Core Ultra 200 | Core Ultra 4000 | Core Ultra 5000 |
| Launch | 2024 | 2027 | 2028 |
| Socket | LGA 1851 | LGA 1954 | LGA 1954 |
| P-Core architecture | Lion Cove | Coyote Cove | Griffin Cove |
| E-Core architecture | Skymont | Arctic Wolf | Golden Eagle |
| Maximum CPU cores | 24 (8P+16E) | 52 (16P+32E+4LP) | TBC |
| Memory support | DDR5 | DDR5 | DDR5 |
| PCIe support | PCIe 5.0 | PCIe 5.0 | TBC |
Three desktop generations sit on one grid: Arrow Lake-S on LGA 1851, Nova Lake-S on LGA 1954, and Razor Lake-S also on LGA 1954. The P-core column reads Lion Cove, Coyote Cove, Griffin Cove. The E-core column reads Skymont, Arctic Wolf, Golden Eagle. The core-count column shows 24, 52, and TBC. The PCIe column shows 5.0, 5.0, and TBC.
The frame holds two confirmed socket generations and one that is still a placeholder. Griffin Cove drops simultaneous multithreading in client parts; the Xeon variant keeps it. Up to 12 Xe3P iGPU cores are the only graphics figure attached to Razor Lake-S. The 64MB BIOS flash on LGA 1954 boards is the gate that lets a 2027 Nova Lake board carry a 2028 Razor Lake part, and a leaked partner slide names Hammer Lake as a further successor on the same socket.
Intel is buying a year of socket stability at the cost of a core-count gap it has not closed. Nova Lake-S ships at 52 cores; Razor Lake-S has no number. A buyer who locks into LGA 1954 in early 2027 is committing to a platform whose second generation is architecturally defined but numerically empty. The 64MB BIOS flash is the only hardware commitment that spans both years, and it is the only figure in the table that is not TBC.
No maximum core count, no TDP, no PCIe generation, no exact quarter within 2028, no SKU names, no pricing. The document does not prove that Razor Lake-S will outperform Nova Lake-S in any measurable way. It proves only that the socket survives and the P-core name changes.
Intel is buying a year of socket stability at the cost of a core-count gap it has not closed. The 64MB BIOS flash is the only hardware commitment that spans both generations, and it is the only figure in the table that is not TBC.
No maximum core count, TDP, PCIe generation, exact 2028 quarter, SKU names, or pricing for Razor Lake-S appears in any document.
The LGA 1954 socket is the only confirmed continuity between Nova Lake-S and Razor Lake-S. Without a core count, TDP, or PCIe generation for Razor Lake-S, a board buyer in 2027 is committing to a platform whose second generation is defined by architecture names but not by performance figures.
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