Vera puts memory bandwidth ahead of core count
Vera's memory plane changes the server equation by keeping latency steady while widening the path.
| Nvidia Vera | |
|---|---|
| memory interface | 1024-bit LPDDR5X-9600 |
| memory bandwidth | 1.228 TB/s |
| PCIe lanes | 88 |
| PCIe bandwidth | 665.5 GB/s |
| L3 cache | 164 MB |
| L3 read bandwidth | 3.35 TB/s |
| NVLink C2C bandwidth | 1.8 TB/s |
| cross-socket core-to-core latency | about 660 ns |
The 1024-bit LPDDR5X interface can move up to 1.228 TB/s, but that ceiling is a fabric number, not a workload result.
The same page lists 88 PCIe lanes at 665.5 GB/s, a 164 MB L3 near 3.35 TB/s, and cross-socket reads above 587 GB/s.
The memory path is wide, yet traffic still splits across local DRAM, cache, and NVLink C2C.
The buyer gains headroom for DRAM-bound tasks, while the board designer must absorb a 1024-bit LPDDR5X plane and SOCAMM2 serviceability.
Cross-socket read-modify-write traffic can reach 780 GB/s, but core-to-core latency spans 87.5 to 199.3 ns inside a socket and about 660 ns across sockets.
Price, exact Olympus core count, and sustained thermal behavior under mixed server load remain unmeasured.
The bandwidth-first framing is the right read, but the unmeasured core count and thermal behavior keep the claim provisional.
After chipsandcheese.com. We did not report this. The pictures, if any, are theirs.
