Xsight Labs documents the E1L DPU with 8, 16, or 22 Arm Neoverse N2 cores, up to 200Gbps over 4x SerDes lanes, and configurable 25 W, 30 W, or 40 W TDP. It also lists up to 2x DDR5-5200 interfaces with inline encryption, line-rate AES-GCM for IPsec offload, and 20 PCIe Gen5 lanes across 6 dual-mode controllers with SR-IOV. A COM Express Type 7 module is the stated form, and it points to switch and storage footprints.

Die Brief reads the E1L as a constrained offload part, not a replacement for the 64-core E1. Those 25 W, 30 W, and 40 W TDP steps put the measurement inside a switch-friendly envelope, but the document does not prove that the 200Gbps path can sustain line-rate encryption at the lowest draw. For a buyer, the useful question is whether the 8-core or 22-core variant can carry the control plane and IPsec load without exceeding the 15 W or 25 W typical draw.

The page leaves out benchmark results, price, ship date, process node, and a named switch or storage platform. Measured power beyond typical draw is also absent, so the TDP and typical figures remain the only power limits. Without those numbers, the claim of lower-power 200Gbps operation is a design target, not a verified result.

Die Brief reads the E1L as a constrained offload part, not a replacement for the 64-core E1. The TDP steps fit a switch envelope, but the document does not prove line-rate encryption at the lowest draw.

The document leaves out benchmark results, price, ship date, process node, and a named switch or storage platform.

The E1L is a lower-power Arm offload module for switch and storage footprints. Its 25 W, 30 W, and 40 W TDP steps are the constraint, but measured line-rate encryption power is absent.