The parasitic RC problem at the standard-cell level is where device physics meets layout reality, and at A7 and A10 nodes the gap between a calibrated transistor model and the actual interconnect stack is where performance predictions go wrong. The constraint is not the transistor itself but the resistance and capacitance that accumulate around it in the cell layout, and those parasitics scale differently across the two architectures being compared.

The system-technology co-evaluation flow from TU Munich, the University of Modena and Reggio Emilia, and Applied Materials chains calibrated device models into optimized standard-cell generation, then pushes through GDS-to-TCAD conversion for 3D parasitic RC extraction. The critical design choice is applying the same device model to both A7 CFET and A10 NSFET, which isolates the parasitic contribution from the device contribution at each level of the design flow. The flow is physics-based and thermal- and aging-aware, meaning the RC numbers are not a single-temperature, single-timepoint snapshot but carry the context of how the chip will actually run and age.

The test vehicle is an AI accelerator, implemented from RTL through GDS. Multiphysics thermal analysis and physics-based bias temperature instability aging evaluation are folded into the same flow, so the parasitic RC numbers carry thermal and aging context rather than being a static extraction. The paper, authored by Benkhelifa, Mayr, Nour Eddine, Padovani, Larcher, and Amrouch, sits on arXiv as 2609.15326, dated September 2026. The comparison spans two different transistor architectures — complementary FET at A7 and nanosheet FET at A10 — which makes the parasitic isolation more meaningful than a same-architecture node-to-node comparison, because the interconnect stack and cell geometry differ between the two.

The abstract excerpt carries no specific RC values, no clock frequency, no power figure, no yield number, and no comparison against a prior STCO methodology. The paper itself is behind a link on Semiconductor Engineering, and the full data set is not in the source text. What is not named: the specific AI accelerator architecture, the standard-cell library size, the thermal profile used in the multiphysics analysis, or the BTI stress conditions. The source is thin — one abstract excerpt and a paper link.

The reusable piece here is the single-device-model-across-two-nodes approach, which lets a foundry or design team attribute performance deltas to interconnect rather than to the transistor itself. Watch for the arXiv preprint to move into a peer-reviewed venue or a DAC or ISSCC presentation, where the actual RC numbers and the AI accelerator's power and frequency will land. The methodology itself — linking device models through cell generation to TCAD extraction to thermal and aging analysis in one flow — is the piece that will get cited regardless of the specific numbers, and the AI accelerator as a test vehicle gives the results a workload context that a synthetic benchmark would not.

The STCO flow links device models through cell generation to TCAD extraction to thermal and aging analysis in one pass, which is the reusable methodology. The AI accelerator workload gives the RC numbers a realistic operating context rather than a synthetic benchmark.