The sub-2nm scaling wall has been the industry's most discussed problem for three years. The consensus: silicon hits a hard floor before anyone can do anything about it. A Nature Communications paper from Carnegie Mellon, MIT, University of Florida, Texas A&M, and collaborators just made that consensus look premature. The authors demonstrated monolayer MoS2 transistors with physical channel lengths below 5 nm on a 4-inch wafer, using a photolithography-based process they call CMOS-compatible. The reaction in the 2D materials community is measured but unmistakable: this is no longer a lab curiosity.

The device is a monolayer MoS2 transistor with a physical channel length below 5 nm. The subthreshold swing is 88 mV/dec, and the on/off ratio exceeds 10 to the 6th power. The process is photolithography-based and described as CMOS-compatible, meaning the patterning step uses standard lithography rather than e-beam or focused ion beam. The team demonstrated integration on a 4-inch wafer, the size at which academic groups typically validate throughput before handing off to a foundry. The paper's tag list references air-gap isolation, suggesting the dielectric stack uses an air gap to reduce parasitic capacitance at these dimensions. No drive current or on-resistance figures appear in the abstract excerpt available through Semiconductor Engineering.

Silicon's theoretical subthreshold swing limit at room temperature is 60 mV/dec. At sub-5 nm channel lengths, silicon devices have historically struggled to stay above 100 mV/dec due to short-channel effects, and the on/off ratio degrades as the channel shrinks. The 88 mV/dec figure here sits below the silicon limit, which the authors explicitly note surpasses both the theoretical subthreshold limit of silicon and state-of-the-art emerging semiconductor transistors at comparable dimensions. The on/off ratio above 10 to the 6th power is the number that matters for logic: it means off-state leakage is low enough that the device can function as a switching element without requiring aggressive gate overdrive. Before this result, the best reported 2D semiconductor transistors at sub-5 nm channels had not simultaneously achieved both metrics.

What the source does not confirm: whether the process is truly complementary, meaning whether p-type MoS2 or a complementary channel material is demonstrated, yield across the 4-inch wafer, drive current, or power consumption. The abstract excerpt available through Semiconductor Engineering is limited to the subthreshold swing and on/off ratio. The paper is open access in Nature Communications, so the full data is available, but the trade press summary does not include those figures. The tag list includes Universidad Politecnica de Madrid and University of Southern California, suggesting a broader collaboration than the four institutions named in the headline.

Watch for two things. First, whether the photolithography-based patterning holds at sub-5 nm resolution on 8-inch or 12-inch wafers, which is where volume manufacturing lives. Second, whether any foundry or IDM engages with the process for a pilot line. The 4-inch wafer result is a throughput proof, not a manufacturing proof. The gap between academic wafer-scale demonstration and foundry integration is typically measured in years, not months.