The 8-core sample 100-000002152-50_Y lists 16 threads in a 2+6 cluster split with 8 MB of L3, and the 6-core sibling 100-000001658-50_Y lists 12 threads in a 1+5 split with 4 MB of L3. Both carry Family 26 Model 224 Stepping 0 and CPU model E0h, while the 10-core Medusa Point 1 uses model 81h with 16 MB of L3. The VideoCardz table places all three on Lenovo systems.

The shared E0h identifier means the 6-core and 8-core are configurations of one die, not two. That constrains the fab: AMD trims cores from a single Medusa Point 2/3 mask rather than spinning a second. Cluster topology is contested. VideoCardz reads 2+6 and 1+5; Mareeswj reads 2+4+2 and 1+3+1. The 1+3+1 sum is five, not six, so that reading fails on arithmetic. The 2+4+2 sum is eight and works, but it implies three clusters where VideoCardz sees two. Until a production SKU ships, the L3 sharing topology is undetermined. Frequency on the same 8-core SKU runs from 2.17 GHz to 5.28 GHz across two Geekbench runs. No number in this table is a production clock.

TDP, memory type, channel count, die size, process node, and per-core L1/L2 breakdown are absent from every document in this set. The production cluster layout and final stepping are not confirmed.

The shared E0h model identifier means the 6-core and 8-core are die configurations, not separate masks, which constrains AMD to yield-trimming on one Medusa Point 2/3 die. The contested cluster topology (2+6 versus 2+4+2) determines L3 sharing, and no production clock or TDP exists in this set.

TDP, memory type, channel count, die size, process node, per-core L1/L2 breakdown, production cluster layout, and final stepping are absent from every document in this set.

E0h unifies the 6-core and 8-core under one Medusa Point 2/3 die. The 2+4+2 reading implies three clusters and a different L3 partition than the 2+6 reading. Frequency spread of 2.17–5.28 GHz on the same SKU confirms engineering silicon. No TDP, memory config, or production stepping is documented.