SpacemiT's V100 carries no price on the Phoronix page that announced it on 19 October 2026. The 46-core server-class RISC-V processor is the first chip SpacemiT claims is fully compliant with the RISC-V server specification. The page names the vendor, the core count, the process node, and the memory interface, but it does not name a configuration SKU, a starting price, or a shipping date. The vendor's number is SpacemiT, and the price of the configuration that number belongs to is not in the document.

The hybrid micro-architecture splits the 46 cores into two populations: six XiangShan Kunminghu V2R2 cores and forty SpacemiT X100 cores. The Kunminghu V2R2 cores are the high-performance tier, the X100 cores the efficiency tier. The document does not state which workload each tier is tuned for, whether the two tiers share a last-level cache, or whether the operating system scheduler will pin threads to a specific tier. The hybrid design is the architectural claim that distinguishes the V100 from a uniform-core server chip, but the document does not explain the scheduling policy or the cache coherency protocol between the two tiers.

The stretch between the two configurations is the socket count. A single V100 delivers 46 cores. Two sockets in one server deliver 92 cores. The document does not state whether the dual-socket configuration doubles the memory channel count to sixteen, whether the PCIe lanes are split between sockets or shared, or whether the TDP scales linearly to 240 watts. Since there is no price, the buyer cannot determine which configuration the vendor intends to sell first, and the 92-core server is a theoretical peak that no chassis has yet housed.

Clock speeds run from 2.2 GHz to 2.4 GHz. The process is 12 nm. The TDP is 120 watts. At 12 nm, the V100 sits behind the leading server silicon, which has moved to 3 nm and 4 nm nodes, and the 120-watt figure is a specification, not a measurement. No lab has drawn power from a V100 and reported a number. The 2.4 GHz figure is a theoretical peak; the document does not state whether it applies to all 46 cores simultaneously or only to the six Kunminghu V2R2 cores. The 2.2 GHz floor is equally unverified.

Memory is eight-channel DDR5-4800. The document does not state the maximum capacity per channel or the total addressable memory. PCIe 5.0 provides 52 lanes, which is sufficient for a single high-bandwidth accelerator plus NVMe storage, but the document does not show a block diagram or a lane allocation table. The buyer cannot determine whether the 52 lanes are split between the two socket interfaces or whether they are all available on a single socket. The DDR5-4800 speed is a memory interface specification; it does not tell the buyer what the memory bandwidth will be under load or what the latency characteristics are.

The RISC-V server specification compliance includes UEFI, ACPI, and SMBIOS support. This is the part that matters for a server buyer: the firmware stack must be present before the operating system loads, and the ACPI tables must describe the hardware correctly for the kernel to enumerate devices. The document states compliance but does not name the firmware vendor, the UEFI version, or the compliance test results. The claim of "first chip fully compliant" is SpacemiT's own, and the document does not cite the specification body or a third-party verification. A server buyer who cannot verify the firmware stack before procurement is buying on a claim, not on a test result.

Phoronix is the only document in this packet. The vendor page at SpacemiT.com is referenced but not independently read. No second desk has published a spec sheet, a teardown, or a benchmark, and the Phoronix piece reports the announcement as a single paragraph of specifications without verifying any figure against the vendor's own documentation. The absence of a second source means that every number in this article is a single-source claim from the vendor, relayed through one wire.

The desk's judgment: the buyer is constrained by the absence of a price, a benchmark, and a shipping date. The 46-core, 12 nm, 120-watt chip is a specification sheet, not a product. What changes for the fab is that 12 nm is no longer a leading-edge node for server silicon, and the 120-watt TDP at 46 cores implies roughly 2.6 watts per core, which is low by server standards where per-core power budgets typically run higher. The buyer cannot know whether the Kunminghu V2R2 cores and the X100 cores share a cache hierarchy or operate on separate memory controllers. The document does not prove that the chip will ship, that it will meet the 120-watt figure under sustained load, or that the RISC-V server specification compliance is verified by a third party.

What is still unmeasured: no benchmark, no price, no SKU, no shipping date, no measured power draw, no memory capacity figure, no cache topology, no thermal characterization. The V100 exists as a set of numbers on a page. The 2026+ date is a window, not a commitment, and the 92-core dual-socket configuration is a theoretical peak that no server has yet housed.

The V100 is a specification sheet, not a product: no price, no benchmark, no shipping date, and no third-party verification of the RISC-V server specification compliance. The 12 nm process and 120-watt TDP at 46 cores place it behind the leading server silicon on both node and power efficiency, and the buyer cannot determine whether the hybrid core tiers share a cache hierarchy.

No benchmark, no price, no SKU, no shipping date, no measured power draw, no memory capacity, no cache topology, and no third-party compliance verification appear in any document.

The 12 nm node and 120 W TDP at 46 cores yield roughly 2.6 W per core, below typical server per-core budgets. The hybrid 6+40 core split lacks a published cache topology or scheduling policy. The 92-core dual-socket configuration is unverified; no chassis, no power measurement, no firmware version, and no third-party compliance test exist in the document.