The test pairs a quad V100 cluster with a single M5 Ultra and two DGX Spark units. Each V100 carries 32GB of HBM2 and 900GB/s of memory bandwidth. The builder milled an A100 heatsink to move 300W per chip and connected the carrier board through PCIe x8.

In the 4-bit Qwen3.8-Flash-Next run, the V100 cluster posts a 40 percent lead over the Spark pair on long prompts and a 230 percent lead over the M5 Ultra. On short prompts it keeps the 40 percent lead over the Spark pair and runs 163 percent faster than the M5 Ultra. For short token generation, the V100s reach 100.6 tok/s while the M5 Ultra reaches 44.5 tok/s.

The reading is that the gap is a topology and software problem. NVLink 2.0 links and HBM2 bandwidth can feed a quantized model, but the packet does not show power, cost per token, latency, or a fair software stack. Buyer constraints sit in carrier-board availability, cooling mods, and PCIe x8 passthrough.

Unmeasured items include batch size, context length, model size, total system power, and the DGX Spark token rate. The document does not show whether the 230 percent gap survives a tuned Apple stack or a larger model.

The gap reads as a topology and software win, not a clean silicon verdict. It does not prove V100 beats M5 Ultra across workloads, and the buyer still pays for carrier board, cooling mods, and power.