The listing pairs 72 MI455X GPUs with 18 EPYC Venice CPUs. Each MI455X and MI430X carries 432 GB of HBM4, and the rack totals 31 TB of HBM4 with 1.67 PB/s of memory bandwidth.

MI430X is listed at up to 288 TFLOPs FP64 and up to 9.2 PFLOPs FP4. The rack listing adds 2.9 exaFLOPS peak OCP MXFP4 and 1.4 exaFLOPS peak OCP MXFP8. That capacity does not prove a rack can hold a frontier model, because the page gives no model size, token rate, or measured power.

Buyer constraint sits in the rack, not the silicon. A 432 GB per-GPU figure lets a lab size KV cache and resident weights, but it does not remove the need for interconnect, cooling, or a fab yield story. The page states a 2026 launch, not a 2025 preview, and it does not prove a measured tokens-per-dollar advantage. Price, measured tokens-per-dollar results, and a physical photograph are absent from the document.

Lead with the fab gap, then move to rack memory and the missing price, tokens-per-dollar, and photo.