Huawei's LogicFolding heat gap
The open question is whether the bonded stack can shed heat, not whether the buffer count falls.
Huawei's filing touts a 50 percent cut in clock buffers for LogicFolding, along with shorter interconnects, a 20 percent drop in typical core wiring length, and critical paths reduced by up to 70 percent.
The desk treats the ceiling as thermal. If the stacked die still needs active cooling, the package becomes denser while the heat path gets harder, and bonding and heat spread must be paid for before any clock gain is banked.
No measured junction temperature, power per area, or thermal resistance appears for the bonded stack, so the buffer cut remains a design claim rather than a thermal proof.
Treat the 50 percent buffer cut as unverified until heat spread is measured.
50 percent clock buffer cut · 20 percent typical core wiring length drop · up to 70 percent critical path · ~1.5 μm copper-to-copper hybrid bonding pitch · Kirin 9050 Pro · compute die and SRAM die bonded
After @austinsemis. We did not report this. The pictures, if any, are theirs. Also filed by Wccftech, TechPowerUp, Tom's Hardware.
