The Ryzen Z3 handheld line is reported to carry a 4+2 CPU core layout and 12 RDNA4m compute units. The VideoCardz post gives no power limit, no clock limit, no node limit, no memory limit, no SKU, and no price. No limit appears in the post. The core and CU counts therefore sit outside any stated boundary.

The 4+2 split implies a small performance island and a larger efficiency island. The document does not prove that split, nor does it prove the island clocks or whether the two cores are full cores. A buyer cannot infer sustained load from core count alone, because memory and power are missing. A fab cannot infer die size from 12 CUs without node and power data.

TDP, process node, memory configuration, SKU, price, and clock range remain absent. The note can be corrected when those fields appear in a later filing. The missing fields decide whether the silicon is a modest handheld unit or a larger raster budget, and whether the power envelope can hold a long frame under real load, and whether the memory path can keep up.

The 4+2 split and 12 CU count define a shape, not a performance envelope. The buyer and fab are constrained by missing clocks, node, and power.

TDP, process node, memory configuration, SKU, price, and clock range are not in the document.

The core and CU counts set the topology, but the document leaves clocks, node, and power open. That leaves sustained load and die size unbounded.