The contract landed on October 1, 2026, and the interconnect stack is already named: LPDDR6, PCIe Gen6, and UCIe-S. SEMIFIVE and Mobilint signed a turnkey development agreement under Korea's K-On-Device AI Semiconductor Technology Development program, a MOTIR-funded initiative that pairs fabless designers with end-user companies and pushes them through to commercialization. The target application is agricultural robotics, processing vision and sensor data in real time in outdoor environments where server connectivity is absent.

The engagement sits at what SEMIFIVE calls the "Spec Hand-off" stage, the earliest point in its turnkey pipeline. Mobilint defines performance targets and specifications; SEMIFIVE handles detailed design, packaging, testing, and mass production. The chip is meant to run high-performance AI inference locally, without a backhaul link to a data center. That constraint shapes the memory and interconnect choices more than any compute-core decision, which the document does not disclose.

UCIe-S, the Standard Package variant of Universal Chiplet Interconnect Express, is the structural backbone here. It lets multiple function-specific chiplets sit in one package and behave as a monolithic die, which matters when you are trying to fit an AI accelerator, a vision frontend, and I/O into a board that has to survive field conditions. LPDDR6 is the latest low-power DRAM standard, and PCIe Gen6 is the high-speed external interface. The document does not state which process node the chiplets will be fabricated on, nor does it give a die size, a TOPS figure, or a power budget.

What this document does not prove is that the chip will meet its own targets. No contract value, no production date, no node, no wattage, no latency number appears anywhere in the filing. The buyer is at the specification stage, not the tape-out stage, and the interconnect choices it has committed to—LPDDR6 and PCIe Gen6 in particular—are not yet in broad mass production. That makes this a roadmap bet dressed as a product announcement. For the fab, the absence of a node assignment means the foundry slot is still open; for the buyer, it means the performance envelope is still negotiable.

The next data point to watch is whether SEMIFIVE publishes a node assignment and a power target once the detailed design phase begins. Until then, the LPDDR6 and PCIe Gen6 references are architectural intent, not silicon. The agricultural-robotics use case will also need a published latency budget for the vision pipeline, because "real time" in a field with variable lighting and dust is a different engineering problem than "real time" in a data center.

The document is a contract, not a spec: no node, no TOPS, no wattage, no production date. LPDDR6 and PCIe Gen6 are not yet in broad mass production, making this a roadmap commitment rather than a silicon milestone.

Mobilint has committed to an interconnect stack (LPDDR6, PCIe Gen6, UCIe-S) before a process node is assigned or a single transistor is drawn. The Spec Hand-off model means the performance envelope is still open; the foundry slot is unbooked. Until a node and power budget are published, the LPDDR6 and PCIe Gen6 references are architectural intent, not a fabrication plan.