NL2GDS, a framework from the University of Bristol and Rutherford Appleton Laboratory, converts natural-language hardware descriptions into synthesizable RTL and GDSII layouts through the OpenLane ASIC flow. The paper, filed as arXiv:2603.05489 in March 2026, evaluates the pipeline on ISCAS'85 and ISCAS'89 benchmark designs. The reported figures are up to 36% area reduction, 35% delay reduction, and 70% power savings relative to baseline designs.

The constraint is the benchmark set. ISCAS'85 and ISCAS'89 are small combinational circuits from the 1980s, and the document does not show the pipeline on a design with sequential logic, memory, or multi-clock domains. The baseline against which the 70% power savings is measured is not named, so the figure is directional rather than a fixed measurement. For a fab or a buyer, the document does not establish whether the generated GDSII passes DRC or closes timing at a foundry node.

The document does not name the LLM engines used in the pipeline, does not specify the baseline designs, and does not report DRC or timing closure results. The behavior of the flow on designs beyond ISCAS'85 and ISCAS'89 is not measured.

The benchmark set limits what the document proves: ISCAS'85 and ISCAS'89 are small combinational circuits, and the pipeline has not been shown on a design with sequential logic or memory. The 70% power savings figure is relative to an unnamed baseline, so it is directional, not a fixed measurement.

The document does not name the LLM engines, does not specify the baseline designs, and does not report DRC or timing closure results.

The pipeline targets OpenLane ASIC flow and ISCAS benchmarks. The document does not report DRC or timing closure, does not name the LLM engines, and does not specify the baseline. The results are bounded by the benchmark set and the absence of foundry-node validation.