500,000 chips is the supercluster target named in the Tom's Hardware page. It does not prove that the Zhenwu V900 can sustain that scale, because the page gives no interconnect, power, memory, or node data. That figure is a cluster target, not a silicon measurement.

Die Brief reads the claim as a constraint on buyers, not on the fab. A 500,000-chip system shifts risk from single-die performance to cluster-level interconnect, thermal headroom, and model sharding. Qwen's 10T-parameter roadmap makes the constraint concrete: without measured bandwidth and power, the buyer cannot separate a strong accelerator from a large, expensive cluster. Missing data sits between the die and the rack.

Still unmeasured are process node, memory capacity, memory bandwidth, clock speeds, power envelope, and interconnect. The document leaves out the numbers that would let a buyer price the cluster or a fab justify the die. No cluster status is shown here.

Die Brief reads the 500,000-chip figure as a buyer constraint, not a fab measurement, because the document lacks interconnect, memory, and power data. The 10T Qwen roadmap raises the stakes, but the page still does not prove a measured system.

The document leaves out process node, memory capacity, memory bandwidth, clock speeds, power envelope, and interconnect.

The 500,000-chip target is a systems constraint: without interconnect, memory bandwidth, and power data, the buyer cannot evaluate die performance or cluster cost. The 10T Qwen roadmap raises the stakes, but the document leaves the silicon unmeasured.