The Nova Lake-S desktop lineup leak lists seven SKUs, with the Core Ultra 9 4970K BFC at the top as a 28-core, 28-thread part. It places the part on a single compute tile with an 8+16+4 P/E/LPE split and a 125 W PL1 base power rating. Wccftech table gives the BFC variants a bLLC ceiling of 144 MB, while non-BFC parts are marked without that cache.

Constraint sits in cache allocation, not core count. Intel can vary bLLC per SKU, so the 144 MB figure is a ceiling, not a guarantee for every BFC part. Buyers cannot infer that the 4970K BFC, 4900 BFC, and 4870K BFC all ship with the same cache, and a fab or board maker cannot use the table to size cache-sensitive workloads or thermal headroom.

No page measured actual performance, IPC, sustained power draw, or the exact bLLC amount for each SKU. Document leaves out process node, launch date, and electrical specs for LGA 1954 or Z990. Until public values appear, the 144 MB ceiling still remains a limit, not a measured allocation for now.

The 144 MB bLLC value is a ceiling, not a per-SKU allocation, so buyers cannot assume every BFC part gets the same cache. The document does not prove performance, power, or exact cache, leaving board and thermal planning incomplete.

No page measured actual performance, IPC, sustained power draw, exact per-SKU bLLC, process node, launch date, or LGA 1954/Z990 electrical specs.

For an engineer, the usable fact is a maximum bLLC envelope of 144 MB on BFC SKUs, while core counts and PL1 values are listed but not validated by measured IPC, sustained power, or per-SKU cache.